1. Field of the Invention
This invention relates to an output buffer circuit and more particularly to a buffer circuit which, when operating in transition between logic levels, maintains a reduced noise level in the power supplies of an integrated circuit incorporating the buffer circuit.
2. Background of the Relevant Art
A buffer circuit used for increasing output drive characteristics is well known. Often, a source cannot provide the necessary drive required by a load. In this case, a buffer circuit may be placed intermediate the source and load, whereby the source drives the buffer and the buffer drives the load. Buffer circuits are thereby often used in situations where a large fan-out number is encountered which would exceed the capability of a non-buffered source. Buffers circuits can also be used to drive output loads that are normally adapted for higher or lower current and/or voltage levels. As such, buffers are often incorporated as voltage/current level converters placed between monolithic integrated circuits having dissimilar logic technology (e.g., TTL-to-CMOS or CMOS-to-TTL). A buffer used as a voltage/current level converter or driver can also suffice as an interface between digital and analog domains. For example, analog switches or relays can be interconnected to receive buffered digital signals from digitally controlled devices such as a microcontroller. Thus, a buffer circuit may or may not provide gain, it may or may not reverse the logic level between the input and output signals; however, a buffer circuit generally does provide current isolation for driving an increased fan-out load or for maintaining compatibility with various output loads.
Conventional output buffer circuits often employ a single stage output driver circuit comprising a single pull-up transistor and a single pull-down transistor. The buffered output signal is formed whenever the pull-up transistor or the pull-down transistor is activated. In order to reduce transient current or crowbar current, the pull-up and pull-down transistors are preferably activated at different times as generally described in U.S. Pat. Nos. 5,025,181 and 4,638,187. U.S. Pat. No. '181 requires mismatched threshold values between the pull-up and pull-down transistors to ensure the transistors are not activated at the same time. Similarly, U.S. Pat. No. '187 utilizes an inverter to delay turn on the pull-up transistor with respect to the pull-down transistor.
During the time in which the single stage driver transistors (either the pull-up or pull-down transistor) are activated, a current spike may occur in the power supplies. Whenever, for example, the pull-down transistor is activated, the output load capacitance is discharged through the current path formed between the load and the ground supply (e.g., VSS). Acceleration of sinking current brings about a positive voltage across the output ground lead inductance proportional to L(di/dt). The positive voltage results in a voltage rise, ground bounce or overshoot of relatively short duration in the ground supply. Similarly, deceleration of sinking current causes a voltage decline, ground droop or undershoot in the ground supply, below VSS voltage. Using a converse example, whenever the pull-up transistor is activated, the output load is charged through the current path formed between the load and the positive supply (e.g., VDD). Acceleration of sourcing current produces a negative voltage across the output ground lead inductance proportional to L(di/dt). The negative voltage results in a voltage drop or undershoot in the positive supply. Undershoot is generally of short duration below the ideal VDD amount. Deceleration of sourcing current causes a short voltage increase or overshoot in the ground supply, above VDD voltage.
In an effort to reduce undershoot and overshoot noise problems occurring on the power supplies of an integrated circuit incorporating the buffer, many conventional buffer circuits utilize two or more output driver stages operating at two different times during an output transition. Examples of disclosures which describe multiple output driver stages include U.S. Pat. Nos. 4,961,010 and 5,103,118. Both U.S. Pat. Nos. '010 and '118 require a resistance element placed intermediate the gate terminals of each pull-up and pull-down driver. The resistance element ensures a delay between the turning on of successive stages; however, the resistance element may dampen or slow down the turning off of opposing stage. For example, during transition from low to high state at the buffer output, it is important that the pull-down transistors be adequately turned off before the pull-up transistors are turned on. Otherwise, the pull-up and pull-down transistors may both be momentarily on thereby allowing transient current to flow directly between the power supplies. Such a result would add considerable power consumption to the device operation. Placing resistive elements within the discharge or charge path of the pull-up and pull-down gate capacitors may add undesirable RC delay in turning off the opposing drivers. Using the rising edge output transition example stated above, the resistive element will oppose rapid change in the pull-down transistor gate. Accordingly, the pull-down transistor may not be able to turn off as rapidly as the first stage pull-up transistor turns on. Still further, prior gate resistive designs do not ensure that all of the opposing drivers are turned off at the same time, or that all the opposing drivers are turned off during the time in which the desired first driver in a series of successive delayed drivers is turned on. If one of the opposing multiple stage driver (e.g., either the first, second or third stage pull-up transistor) remains momentarily on during the time in which the desired driver (e.g., the first stage pull-down transistor) is turned on, then an undesirable direct current path between positive supply and ground supply may occur.
As defined herein, "opposing drivers" refers to the pull-up transistors which are configured opposite the pull-down transistors or, conversely, refers to the pull-down transistors which are configured opposite the pull-up transistors. In addition, the term "desired driver" refers to the driver which is currently activated. If, for example, the desired driver is one of the stages of pull-down transistors, then the opposing drivers are the multiple stages of pull-up transistors. As further defined herein, "overshoot" is a positive voltage spike induced on either the first or second power supplies. Conversely, "undershoot" is a negative voltage spike induced on either the first or second power supplies. First power supply is defined as the most positive power supply (e.g., VDD), whereas the second power supply is defined as the most negative power supply (e.g., VSS or ground). Overshoot upon the first power supply is caused by decelerating sourcing current delivered from the first power supply to the load device. Overshoot upon the second power supply is caused by accelerating sinking current delivered to the second power supply from the load. Undershoot upon the first power supply is caused by accelerating sourcing current delivered from the first power supply to the load. Undershoot upon the second power supply is caused by decelerating sinking current delivered to the second power supply from the load device.